An attempt has been made to increase the breakdown voltage of a semiconductor device including a MOS field effect transistor (metal oxide semiconductor field effect transistor, MOS FET).
FIG. 6 is a schematic sectional view of a prior art semiconductor device including MOS FETs (see Japanese Unexamined Patent Publication No. 2003-46082).
A semiconductor layer 54 including N-type drift layers (N-type pillar layers) 52 and P-type RESURF (reduced surface field) layers (P-type pillar layers) 53 is provided on an N++-type semiconductor substrate 51. The drift layers 52 and the RESURF layers 53 are recurrently arranged in alternate relation in a direction parallel to the semiconductor substrate 51 to provide a so-called super junction structure.
A plurality of trenches 55 are provided in the semiconductor layer 54 as extending thicknesswise of the semiconductor layer 54 and having a depth such as to reach an interface between the semiconductor substrate 51 and the semiconductor layer 54. The trenches 55 each have interior side walls generally perpendicular to the semiconductor substrate 51, and are generally equidistantly arranged parallel to each other. The interior walls of the trenches 55 are each covered with an oxide film 63, and the insides of the trenches 55 are each filled with a buried layer 64 such as of polysilicon or a dielectric material.
The drift layers 52 are each disposed alongside the trench 55. The RESURF layers 53 are each disposed between a pair of drift layers 52 disposed alongside each adjacent pair of trenches 55. The RESURF layer 53 contacts the pair of drift layers 52 and the semiconductor substrate 51.
N-type regions 56 are each provided on the drift layer 52. P-type base layers 57 are each provided on the RESURF layer 53 in contact with the adjacent N-type regions 56. N-type source regions 58 are provided in a surface portion of each of the base layers 57.
Gate electrodes 60 are each disposed in opposed relation to a region including portions of the base layers 57 between the N-type regions 56 and the source regions 58 with the intervention of an insulative film 59. A source electrode 61 is provided in contact with the source regions 58 and the base layers 57. A drain electrode 62 is provided on a back surface of the semiconductor substrate 51 (opposite from a surface of the semiconductor substrate formed with the gate electrodes 60 and the source electrode 61).
The semiconductor device is used in such a state that, with one of the source electrode 61 and the drain electrode 62 connected to an external load, a predetermined voltage from a power source is applied between the external load and the other of the source electrode 61 and the drain electrode 62. The applied voltage provides a reverse bias to PN junctions defined between the RESURF layers 53 and the drift layers 52.
In this state, the gate electrodes 60 are kept at a proper potential (the MOS FETs are turned on), whereby electric currents flow between the source electrode 61 and the drain electrode 62. At this time, channels are formed in the portions of the base layers 57 between the N-type regions 56 and the source regions 58 in the vicinity of interfaces between the insulative films 59 and the base layers 57. Thus, the electric currents flow from the drain electrode 62 to the source electrode 61 through the semiconductor substrate 51, the drift layers 52, the N-type regions 56, the portions of the base layers 57 adjacent to the interfaces between the insulative films 59 and the base layers 57 (the channels) and the source regions 58.
At this time, a reverse bias resulting from voltage division between the external load and the ON-resistances of the MOS FETs is applied to the PN junctions defined between the RESURF layers 53 and the drift layers 52. However, depletion layers occurring due to the reverse bias spread to a negligible extent, so that carrier (electron) paths are present in the respective drift layers 52.
Next, an explanation will be given to a state to be observed when the MOS FETs are off, i.e., when the gate electrodes 60 are not kept at the proper potential. In this case, the channels are not formed, so that no electric current flows in the MOS FETs. Therefore, the whole source voltage is applied as a reverse bias to the PN junctions defined between the drift layers 52 and the RESURF layers 53. Hence, the depletion layers immediately spread into the drift layers 52 and the RESURF layers 53 from interfaces S between the drift layers 52 and the RESURF layers 53, whereby the drift layers 52 and the RESURF layers 53 are completely depleted. This theoretically realizes a higher breakdown voltage.
However, the RESURF layers 53 also contact the semiconductor substrate 51 of the N++-type conductivity. Therefore, when the reverse bias voltage is applied to the PN junctions defined between the drift layers 52 and the RESURF layers 53, depletion layers also spread into the RESURF layers 53 and the semiconductor substrate 51 from interfaces between the RESURF layers 53 and the semiconductor substrate 51.
At this time, the depletion layers spread in regions adjacent to the interfaces S between the drift layers 52 and the RESURF layers 53 and in regions adjacent to the interfaces between the semiconductor substrate 51 and the RESURF layers 53 in different manners, because the semiconductor substrate 51 and the drift layers 52 have different impurity concentrations. Therefore, when the semiconductor device is off, strong electric fields locally occur in the depletion layers, so that the electric currents flow in strong electric field regions. Therefore, the breakdown voltage of the semiconductor device is not satisfactory in practice.